The FPD LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 ...

This is my take on the FabGL dev kit, designed into the form factor of a RC2014 card with the intention of implementing a serial terminal. FabGL is an excellent graphics/UI/Human Interface library for ...