The FPD LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Data Enable, and Pixel Clock to a FPD LVDS compliant display panel via 3 or 4 ...
Leave any questions on the GitHub issues or on the Discord channel below. If you want to add your language to the app, please translate assets/locale/en.json. I can translate it by Google translator, ...