PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace. According to the “PCI ...

TMR is not a new idea in the world of ASIC design. It was published as far back as 1962 in the IBM Journal of Research and ...

This collaboration highlights GUC's commitment to deliver comprehensive and innovative design solutions, enabling customers ...

A jury in Wilmington, Delaware, has found that Qualcomm’s latest AI-PC processors – based on the ARM instruction set – are ...

This funding will support the continued development and demonstration of Strategic Radiation Hardened (SRH) high reliability ...

Process: GF 28nm SLP 1.0V/1.8V CMOS process Supply voltage: 1.62V<=AVDD18(DVDD18)<=1.98V,0.9V<=AVDD10(DVDD10)<=1.1 Mos device type: egpfet, egnfet, pfet, nfet Operating current: AVDD18<4mA(1Ghz) ...

The issue of quantum readiness is gaining momentum, as suppliers and manufacturers realize the importance of the transition ...

Low-power design is critical, especially for chips inside battery-operated IoT devices that must support applications for ...

NetTimeLogic’s PTP Timestamp Unit is an implementation of a single port Frame Timestamp Unit (TSU) according to IEEE1588-2008 (PTP). It detects PTP frames on a (R)(G)MII tap and timestamps PTP event ...

As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. System and chip designers ...

Multiprotocol SerDes PMA supporting variety of interfaces.

VeriSilicon (688521.SH) today announced the launch of its latest Vitality architecture Graphics Processing Unit (GPU) IP ...